The present invention relates to methods for performing block management, erase operations and program operations in a nonvolatile memory device.
Recently, demand for nonvolatile memory devices has increased. Nonvolatile memory devices are electrically programmable and erasable and do not need a refresh function for periodically refreshing data.
In general, a nonvolatile memory device includes memory cell arrays in which cells for storing data are arranged in the shape of a matrix and page buffers which write data into specified cells of the memory cell arrays or read the data stored in specified cells of the memory cell arrays. The page buffers include pairs of bit lines which are connected with specified memory cells, registers for temporarily storing data to be written into memory cell arrays or the data read from the specified cells of memory cell arrays, sensing nodes for sensing the voltage levels of specified bit lines or specified registers, and bit line select sections for controlling the connection between the specified bit lines and the sensing nodes.
In the nonvolatile memory device configured as described above, operation is performed by the unit of a block in which unit memory cell arrays are included. If a failure occurs while testing blocks, the entire memory device is not disposed. Instead, processing is conducted such that bad (i.e., improperly functioning) blocks are not used. This is called bad block management. A bad block includes a cell which is not programmed over a specified threshold voltage even though a is plurality of programming and verifying operations has been performed. In the conventional nonvolatile memory device, if a failure occurs in a circuit during a test, the fuse included in the block switch of a corresponding block is blown such that the corresponding block is not selected. However, the fuse included in each block and a PMOS transistor for supplying a high level voltage to a specified node to blow the fuse occupy a substantial space in the circuit.